In the field of communication devices or information processing devices, a device having a device configuration called as “chassis type” (hereinafter, referred to as “a chassis type device”) is used. The chassis type device includes a housing (may also be called as “a shelf”) having a plurality of slots and a plurality of devices called as “modules” or “cards” inserted into the plurality of slots.
The “modules” or “cards” are devices (hereinafter, referred to as “a card device”) having electric and electronic components, such as a semiconductor device, mounted thereon for a predetermined function. The chassis type device can exhibit an intended function by inserting the plurality of card devices into the slots and electrically connecting between card devices to integrate functions included in each card device. In the “chassis type” device, inserting (connecting) a card device into the housing enables to utilize a function contained in the card device. Therefore, the “chassis type” device is also called as a plug-in card storage device in a “plug-in system”.
For example, a chassis type switch, which is one of communication devices of a chassis type, includes a housing, a card device (called as “a switch card” or “a switch fabric”) responsible for a switching function that links between a card device (called as “an interface card” or “an interface module” (hereinafter, represented as an interface card (IF card))) having an interface function of the communication device and a plurality of interface cards and transfers a signal received at each interface card to an intended interface card, and a card device (referred to as “a control card”) including a controller responsible for behavioral control of the switch card and the interface card.
In such a chassis type switch, a number of ports storable for chassis type switches can be increased by adding an interface card to an empty slot. Alternatively, a new function based on a new control method can be added by exchanging the control card.
In recent years, with the progress of a miniaturization technique of semiconductor circuits, soft errors in an FPGA (field-programmable gate array) or RAM (read only memory) circuit is becoming a problem. A soft error is a phenomenon in which a RAM or a logic circuit inside an LSI (large scale integration) malfunctions for some reason (for example, cosmic rays or a rays). Such a soft error is not a complete failure of the circuit and the soft error state can be resolved by resetting, for example, the power supply. In this respect, it is distinguished from “a hard error” representing a complete failure of a circuit. Such a problem of soft errors can occur for a card device mounted on a chassis type device.
As a technique related to the present application, there is a technique of stopping an FEC (forward error correction code) decoder not in use by information from a station side device sending data to reduce power consumption on a receiving side (for example, refer to Japanese Laid-open Patent Publication No. 2011-15278).
In addition, there is an integrated circuit device having an ECC function mounted thereon that can be subjected to integrated error correction code (ECC) processing to a large number of memory macros while suppressing an increase in the area (for example, refer to Japanese Laid-open Patent Publication No. 2008-90419).
Still in addition, there is a technique of providing optimal signal transmission processing by measuring properties of a transmission circuit in a reception error rate and a reception signal level of a fixed pattern signal before starting data communication to feedback the measurement result to the sending side and also to reestablish signal processing on the receiving side (for example, refer to Japanese Laid-open Patent Publication No. 2006-332920).
Yet in addition, there is a technique that is provided with a memory, a processor, an automatic error detection/correction circuit, and software monitoring occurrence of error detection and determining whether or not to issue a warning and the nature of the warning by comparing the frequency of detection with a regular frequency of soft errors to the used memory device and that issues an appropriate warning from an online memory monitoring system when a probability of occurrence of memory errors of a plurality of bits is more than a predetermined threshold (for example, refer to Japanese Laid-open Patent Publication No. 10-55320).
Further, there is a technique in which a control section controls switch timing of an optical switch and send timing of a plurality of subscriber side devices in such a manner that the optical switch does not receive an upstream communication signal from the plurality of subscriber side devices during a switching transition period from the start to finish of switching by the optical switch from a communication circuit outputting a downstream communication signal received from an optical line unit before switching to a passive optical network to a communication path outputting a downstream communication signal received from an optical line unit after switching to a passive optical network (for example, refer to Japanese Laid-open Patent Publication No. 2010-147801).